1. Field of the Invention
The present invention generally relates to coefficient multiplying circuits and, more particularly, is directed to a coefficient multiplying circuit in which the number of synthesizers can be reduced.
2. Description of the Prior Art
A conventional coefficient multiplying circuit of a shift-add type will hereinafter be described with reference to FIG. 1.
In FIG. 1, reference letter Tin designates an input terminal which is supplied with an input parallel binary signal. Reference letters BS.sub.0, BS.sub.1, BS.sub.2, . . . , BSm designate (m+1) bit shifters which are commonly supplied with the input parallel binary signal from the input terminal Tin, wherein numbers N.sub.0, N.sub.1, N.sub.2, . . . , Nm of bit shifts performed by the respective bit shifters BS.sub.0, BS.sub.1, BS.sub.2, . . . , BSm are made different from one another. The number of these bit shifters and the numbers N.sub.0, N.sub.1, N.sub.2, . . . , Nm of bit shifts are determined by binary coefficients which are multiplied with the input parallel binary signal. In this example, N.sub.0 &lt;N.sub.1 &lt;N.sub.2 &lt;. . . &lt;Nm is satisfied.
Outputs from the bit shifters BS.sub.0, BS.sub.1 are supplied to an adder AD.sub.1 to be added to each other, an output from the adder AD.sub.1 and an output from the bit shifter BS.sub.2 are supplied to an adder AD.sub.2 to be added to each other, . . . , and an adder ADm at the last stage outputs a binary signal derived by multiplying a binary coefficient with the input binary signal and supplies the same to an output terminal Tout.
Next, the relation between a decimal coefficient and a binary coefficient will be described. A coefficient A expressed by a decimal number is given by the sum of powers of two, where the power numbers are different from one another, as shown in the following equation: EQU A=2.sup.N0 +2.sup.N1 +2.sup.N2 +. . . +2.sup.Nm ( 1)
where N.sub.0 .noteq.N.sub.1 N.sub.2 .noteq.. . . .noteq.Nm and EQU N.sub.0 &lt;N.sub.1 &lt;N.sub.2 &lt;. . . &lt;Nm
At this time, Nm is a value which satisfies the following condition: EQU 2.sup.Nm .ltoreq.A&lt;2.sup.Nm+1 ( 2)
To derive powers of two constituting the coefficients A, B expressed by decimal numbers, supposing A.sub.0 =A, B.sub.0 =B, N satisfying the following equations is calculated as shown in FIGS. 2A and 2B: EQU 2.sup.Nm .ltoreq.A.sub.0 &lt;2.sup.Nm+1 EQU 2.sup.Nm .ltoreq.B.sub.0 &lt;2.sup.Nm+1
Then, irrespective of whether A.sub.0, B.sub.0 are close to 2.sup.Nm or 2.sup.Nm+1, A.sub.0 -2.sup.Nm =A.sub.1, B.sub.0 -2.sup.Nm =B.sub.1 are substituted for A.sub.0, B.sub.0, and the same operation is repeated.
Considering 1, 2, . . . , 1024 as coefficients expressed by decimal numbers, the number of coefficients which respectively make the number of adders as 0, 1, 2, ..., 9 are as shown in the left side of the table shown in FIG. 3 from which it is understood that there are many coefficients which require a large number of adders.